Today's advanced integrated circuit (IC) designs involve description of the circuits using a high-level description language or hardware description language (HDL), such as the Very High-Level Design Language (VHDL) (alternatively VHSIC very high speed integrated circuits hardware description language) or Verilog®. Synthesis tools then use this description to generate a circuit description for the electrical implementation of the IC. This lower level description includes gates, ports, memory, multiplexers and the like. Eventually, the IC design is further reduced to a transistor level description that is used in the actual layout of the IC.
A logic description written in VHDL or Verilog is an RTL (register transfer level) description, i.e. VHDL and Verilog are HDLs (hardware description languages) in which an RTL description can be written. An RTL description is mapped into a gate level description or netlist. Netlists can be physical or logical. An RTL description (or a VHDL description) can be mapped onto a CPLD (complex programmable logic device), FPGA (field programmable gate array) or full custom chip at the logic gate (logic gates and wires as schematic symbols) and finally at the transistor level and maskmaking level (transistors and wires as geometries and layers on an integrated circuit), using an EDA (electronic design automation) tool, i.e. EDA software. The netlist is then used for verification that the physical implementation of the integrated circuit matches the RTL description.
High-level description languages may use various branching conditions such as all variants of case blocks, if-then-else blocks, ternary operators, array indexes, VHDL ‘when’ constructs, and VHDL ‘with’ constructs. Typically portions of such high-level description are eventually transformed into multiplexers (also known as muxes). An exemplary multiplexer 100 (also known as a mux) is shown in FIG. 1. The multiplexer has a plurality of inputs 110-1 through 110-N, N being an integer starting at ‘2’, control signals 120-1 through 120-M, M being an integer starting at ‘1’, and an output 130. The inputs 110-1 through 110-N may comprise of a signal or a bus, a bus being a combination of two or more signals. The output 130 of the multiplexer 100 can be a single bit, in the case of a multiple input single bit output multiplexer, or a multibit bus in the case of a multiple bus multiplexer.
In the process of transformation from a high-level description language of a circuit to a low-level description of the same circuit, multiple multiplexers may be created. The creation of many multiplexers may be inefficient in many ways, including, for example, routing congestion, larger IC area, and increased power consumption, to name but a few. It would therefore be advantageous to provide a solution that would capture the problems with the various multiplexing structures in the process of conversion from a high-level description of a circuit to the low-level description thereof.